Performance specifications high-speed digital devices assure their proper interface with other devices. One of the most common specifications is the output delay parameter TDOUT. This output delay parameter TDOUT is the minimum to maximum delay on the sending device from the clock input to an internal register to the arrival of output data at the sending device pin. To permit tight control of the synchronization between the clock signals on two interfacing integrated circuit chips, the clock for the second chip is often derived directly from the clock of the first chip.
The receiving device often has corresponding specifications requiring that the input data arrive between specified limits of setup time TSETUP and hold time THOLD. This assures that the clock of the receiving device will register the desired data.
FIG. 1 illustrates an example of the output delay and input setup and hold time paths for a common scenario. Output 115 of chip A has the propagation delay time TPD from system clock input 109 to output 115. This propagation delay time TPD includes: the delay in input clock buffer 110; the delay in register element 102; and the delay in output buffer gate 103. Clock 118 for chip B is derived directly from clock 109 of chip A via buffers 106 and 108.
The combination of output delay TDOUT 114 of chip A and the limits between setup time TSETUP 117 and hold time THOLD 119 of chip B determine whether the interface works properly. Typically the delay of gates 105 and 108 are adjusted to meet the interface specifications. Trimming the delays of gates 105 and 108 result in a match of arrival of data at node 113 and clock node 116 for data capture in register 112. Testing for successful adherence to these specifications places a very severe burden on the test machine for the integrated circuit. This burden gets heavier as the chips operate at increasingly higher clock rates. In addition, chip pin counts are increasing to accommodate wide buses and flexibility through the use of large numbers of control pins. This results in severe test challenges and high test cost.
There is a trend to employ tuning adjustments in the critical parameters to guarantee the AC performance needed at the highest possible yield. These challenges increasingly employ test circuitry on the chip itself. These chips also enable adjustment of the timing to cause a device that would otherwise fail to work properly after the adjustment.
The most successful manner for timing adjustment of the output buffer configuration in current technology adjusts of transistor size in both P-channel and N-channel transistors of the buffer. FIG. 2 illustrates an example prior art circuit employing this basic principle. Binary weighted P-channel transistors 201 are optionally switched into operation according to binary code OVTP 202. Similarly, binary weighted N-channel transistors 203 are optionally switched into operation according to binary code OVTN 204.
Utilizing the adjustments available in FIG. 2 takes many forms. The adjustment could be determined by a totally empirical approach. The output gate performance is evaluated on the chip using a mid-range value of the bit codes, and adjusted to obtain the best results. More sophisticated approaches have been developed using more direct information on the proper code.
It is desirable to develop propagation delay information on a particular chip undergoing adjustments before making arbitrary adjustment choices. Each chip has special properties pertinent to the details of its fabrication process. Normal semiconductor manufacturing results in a distribution of transistor characteristics, yielding transistors of varying drive strengths. Using these transistors results in a distribution of gate delays. Thus adjustment is needed to yield the best performance.
Normally some measurements are made on the output performance on the chip as illustrated in FIG. 1. The key to adjustments for performance improvement lie in making a connection between data taken on a chip to the expected performance of a standard gate also measured on the chip.